1. Field of the Invention
The present invention relates generally to systems and methods for distributing a data signal along a “long wire” in an integrated circuit.
2. Description of Background Art
There is an increasing interest in high-speed microprocessors, such as microprocessors with a clock cycle frequency greater than one Gigahertz. In these microprocessors it is desirable to communicate data signals as quickly as possible. However, as clock cycle frequencies increase, the transition times (rise and fall times) become more important. It is advantageous to have the data signal transition from ground to a logic logical “1” and vice versa as fast as possible. Shorter transition times allow more time for the receiving logic to process the data signal. This may lead to overall faster systems with higher frequencies.
In conventional integrated circuits, data signals may degrade when transmitted over a distance. Degradation may take the form of increasingly slower transition times, effectively spreading out the data signal. Often, the data must be transmitted farther than can be transmitted without signal boost or other transmission assistance. To maintain data integrity and speed, a buffer, or repeater, is used to boost and amplify the data signal as it propagates down a long wire. This helps maintain relatively fast transition times for the data signal.
In conventional integrated circuits, a buffer is implemented as one or two inverters in series. In a conventional CMOS design topology, the inverters are each formed from an NFET and a PFET transistor connected in series between a logical “1” power bus and ground (logical “0”). While effective at aiding the data signal along a long wire, these conventional buffers have a basic inefficiency. Because of the simple design, both transistors in each inverter must be rather large in order to provide enough current to propagate the data signal along the long line in short transition times. However, in such conventional designs, there is a period of time around a transition when both the NFET and the PFET may be active as one FET switches on and the other FET switches off. During this time of dual activity, one of the FETs acts as a parasitic load on the other, slowing its switching, as well as creating a short from power to ground. This short is commonly known as a crowbar current. Both the crowbar current and the parasitic load cause the inverter to be slower in transitioning from a logical “0” to a logical “1” and vice versa. This increases the rise and fall times, and adds latency to the system. Furthermore, it is inefficient from an energy-usage standpoint.
Other conventional buffer topologies include using a split drive buffer that includes an inverter pulse generator for each edge of an input data signal and a PFET and NFET in series to drive an output signal. For instance, one pulse generator focuses on recognizing a logical “0” to logical “1” transition and reacts quickly to drive the output PFET. The second inverter pulse generator focuses on the logical “1” to logical “0” transition to drive the output NFET. Each pulse generator relies on the delay through an inverter to end the pulse. Thus, each pulse generator turns on its associated PFET or NFET for a short time, creating a pulse-controlled output. By utilizing a pulse, the PFET and NFET are prevented from being switched on together, thus eliminating the parasitic load and crowbar current inefficiencies found in the single or double inverter buffer described above. Since the FETs are turned on for a short time only, the output from the buffer is typically tri-state. In some circuits, a keeper circuit may be used to stabilize the output while the buffer is in tri-state.
Additional modifications to this design include using a skewed gain chain after the pulse generator in order to provide a higher current to turn on the PFET and NFET quickly. However, in both configurations, the inverter pulse generators introduce some delay penalty in the system. The inverter pulse generators also create a higher input capacitance with associated higher input power requirement. In longer data signal paths, this may require the buffers to be placed closer together to avoid excessive data signal degradation due to the additional capacitance and power requirements. Finally, inverter pulse generators fail to operate at slow input edge rates (i.e. when rise and fall times are long). As noted above, this further limits the effectiveness of the buffers, and requires additional buffers to be placed on a long wire in order to ensure that the transition times do not increase beyond the ability of the buffer to respond to the transition.
Therefore, what is needed is a data signal buffer which: 1.) decreases transition times; 2.) is energy efficient; 3.) can correctly respond to data signals with a long transition time; and 4.) requires installation of fewer buffers for a given long-wire length.